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July 11 - 13, 2022 | Portland, Oregon + Virtual
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Wednesday, July 13 • 3:50pm - 4:30pm
Lessons Learned from Hardware Acceleration Initiatives for Ceph-specific Workloads - Harry Richardson & Lionel Corbet, SoftIron

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For a number of years SoftIron has been researching a number of approaches for accelerating workloads in Ceph. This has entailed building an underlying framework for hardware acceleration and dedicated communication protocols. Designed to be generic, it gives us a flexible platform to run applications or workloads in hardware with the appropriate design - in an entirely transparent way to a Ceph user. Our first workload was erasure coding, and we’ve now moved on to looking at compression algorithms with specific Ceph workloads. In this talk we’ll cover the original design goals for our project, walk through our architecture and design, and demonstrate how it has evolved over time.


Harry Richardson

Chief Scientist, SoftIron
Harry is Chief Scientist at SoftIron. His background is in security, cryptography and high-performance computing. His primary obsessions are creating elegant APIs and ensuring that every network protocol has a version field.
avatar for Lionel Corbet

Lionel Corbet

Principal FPGA Engineer, SoftIron
Lionel is Principal FPGA Engineer at SoftIron. He has a background in logic synthesis and static timing analysis; both as application engineer and R&D engineer. Lionel previously worked at Altera and has been involved in taking multiple FPGAs to market.

Wednesday July 13, 2022 3:50pm - 4:30pm PDT
Regency Ballroom C